1. Field of the Invention
The present invention relates in general to a liquid crystal display device and, more particularly, to an array substrate having a plurality of thin-film transistors that compensates for a falling time delay caused by an RC delay of a gate pulse.
2. Discussion of the Related Art
Until recently, a cathode-ray tube (CRT) has generally been used for display systems. However, use of flat panel displays is increasingly common, because of their small depth, desirably low weight, and relatively minimal power consumption. Presently, thin-film transistor-liquid crystal displays (TFT-LCDs) are being developed with high resolution and small depth.
Liquid crystal display (LCD) devices generally make use of optical anisotropy and polarization properties of liquid crystal molecules to control alignment orientation. The alignment direction of the liquid crystal molecules can be controlled by application of an electrical field. Accordingly, when an electrical field is applied to liquid crystal molecules, the alignment of the liquid crystal molecules changes. Since refraction of incident light is determined by the alignment of the liquid crystal molecules, the display of image data can be controlled by changing the applied electrical field.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin-film transistors and pixel electrodes arranged in a matrix form, are of particular interest because of their high resolution and superior display of moving images. Because of their light weight, thin profile, and low power consumption, LCD devices have wide application in office automation (OA) equipment and video units. A typical LCD panel may include an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a “color filter substrate,” may include a common electrode and color filters. The lower substrate, commonly referred to as an “array substrate,” may include switching elements, such as thin-film transistors (TFTs), and pixel electrodes.
FIG. 1 is a cross-sectional view of a pixel of a related art LCD panel in an active matrix LCD. FIG. 2 is a schematic diagram showing the main components of a related art active matrix LCD.
As shown in FIGS. 1 and 2, an LCD panel 10 includes upper and lower substrates 20 and 30, respectively, and a liquid crystal (LC) layer 50 interposed therebetween. The lower substrate 30 is transparent and includes a thin-film transistor (TFT) T as a switching element that transmits a voltage to a pixel electrode 32 disposed over the lower substrate 30 to change the orientation of the LC molecules. The pixel electrode 32 applies an electrical field across the LC layer 50 in response to signals applied to the TFT T. The lower substrate 30 is commonly made of glass. Moreover, the lower substrate 30 includes a storage capacitor CST that maintains the voltage on the pixel electrode 32 for a period of time. A plurality of gate lines 36 are disposed over the lower substrate 30 in a transverse direction, as shown in FIG. 2, and a plurality of data lines 40 are also disposed over the lower substrate 30 in a longitudinal direction substantially perpendicular to the gate lines 36.
The upper substrate 20 includes a color filter 22 for producing a specific color and a black matrix 26 for preventing light leakage of the LC layer 50. A common electrode 24 is disposed to cover the color filter 22 and the black matrix 26. The common electrode 24 serves as an electrode for producing the electrical field across the LC layer 50 (in combination with the pixel electrode 32). The common electrode 24 may be arranged over a pixel region P, which corresponds to a display area. The color filter 22 may be a red, green or blue color filter. The black matrix 26 is disposed among the red, green and blue color filters and protects the TFT T from external incident light. To prevent leakage of the LC layer 50, the substrates 20 and 30 may be sealed by a sealant.
As shown in FIG. 2, the pixel regions P are defined at the intersections of the gate lines 36 and the data lines 40 in a matrix. Each TFT T and the pixel electrode 32 are disposed in a corresponding pixel region P. Further, the common electrode 24, the pixel electrode 32 and the interposed LC layer 50 define a liquid crystal (LC) capacitor CLC. The storage capacitor CST is connected in parallel to the LC capacitor CLC within the pixel region P. The storage capacitor CST is necessary to compensate for the problem of parasitic capacitance. Further, as shown in FIG. 1, first and second polarizers 28 and 34 are formed on outer surfaces of the upper and lower substrates 20 and 30, respectively.
Referring again to FIG. 1, an image is displayed by the combination of red, green and blue color filters by light passing through the first and second polarizers 28 and 34 and the LC layer 50. A backlight device 60 is disposed under the lower substrate 30 and emits artificial light toward the LCD panel 10. Since the LCD panel 10 does not illuminate by itself, the backlight device 60 is required to provide sufficient brightness. The upper and lower substrates 20 and 30 can include alignment layers (not shown) in their inner surfaces adjacent to the LC layer 50 in order to define the initial arrangement of the liquid crystal molecules.
As shown in FIG. 2, a gate driver 38 is connected to the gate lines 36 and is formed in a periphery of the lower substrate 30. The gate driver 38 sequentially applies a gate pulse to the gate lines 36. A data driver 42, which is connected to the data lines 40, is disposed in a top periphery of the lower substrate 30. The data driver 42 applies a data pulse to the data lines 40. The gate pulse applied to the gate lines 36 turns on the TFTs T, and the data pulse applied to the data lines 40 is an LC driving voltage that changes the arrangement of the liquid crystal molecules.
FIG. 3 is a partial enlarged view of a circuit diagram illustrating the related art active matrix LCD of FIG. 2.
In FIG. 3, the TFT T, which is formed in the pixel region P, includes a gate electrode “g” that is connected to the gate line 36, a source electrode “s” that is connected to the data line 40, and a drain electrode “d” that is connected to the LC capacitor CLC. The TFT T is turned on or off by the applied gate pulse, thereby acting as a switch applying the data pulse to the LC capacitor CLC.
The LCD panel 10 of FIG. 1 displays images frame-by-frame. As shown in FIG. 2, the gate driver 38 applies the gate pulse to sequentially scan the G1 to Gm gate lines. The data driver 42 applies the data pulse, which corresponds to the gate pulse, to all data lines D1 to Dm, respectively. For example, when the gate pulse is applied to the Gm-1 gate line, the data pulse is applied to the D1 to Dm data lines. Thus, the TFTs T1 to Tm connected to the Gm-1 gate line are turned on. Then the data pulse applied to the D1 to Dm data lines is delivered to the designated LC capacitor CLC of the pixel P. The LC capacitor CLC holds an intended voltage applied through the data lines, and the intended voltage changes the arrangement of the liquid crystal molecules.
Meanwhile, when the gate pulse is applied to the gate line 36, the gate pulse travels from left to right, as shown in FIG. 2, through the gate line 36. However, since the gate line 36 is conductive and has its own electrical resistance and capacitance, a pulse waveform becomes different from the first addressed waveform as it travels to the right.
FIGS. 4A and 4B are graphs illustrating a gate pulse and a data pulse which are applied to the different TFTs T1 and Tm connected to the Gm-1 gate line of FIG. 3. FIG. 4A corresponds to the first TFT T1 to which the gate pulse G(N) is first applied, and FIG. 4B corresponds to the last TFT Tm to which the gate pulse G(N) is applied through the Gm-1 gate line. The Gm-1 gate line is selected for simplification of description. The description hereinafter can be adapted to the other gate lines G1 to Gm. Further, as shown in FIG. 3, the TFTs connected to the Gm-1 gate line are denoted as T1 to Tm from left to right.
In FIGS. 4A and 4B, D(N) denotes the data pulse applied to the TFT T1 and the TFT Tm. D(N−1) denotes the data pulse applied to the TFTs connected to the Gm-2 gate line prior to the Gm-1 gate line. D(N+1) denotes the data pulse applied to the TFTs connected to the Gm gate line next to the Gm-1 gate line.
The gate pulse G(N) and the data pulse D(N) have a square waveform and thus have a rising slope to initially maintain a predetermined voltage in the middle, and have a falling slope in a last step. Each time the gate pulse G(N) applied to the Gm-1 gate line rises, the TFTs T1 to Tm are turned ON if the voltage is boosted over a threshold voltage Vth. Thereafter, the date pulse D(N) is applied to the LC capacitor CLC; then the electrical charges are stored in the LC capacitor CLC. When the gate pulse G(N) falls below the threshold voltage Vth, the thin-film transistors T1 to Tm are turned OFF, and the data pulse D(N) is shut down from the KC capacitor CLC.
In FIGS. 4A and 4B, a section Ta denotes a charging time in which the data pulse voltage is held by the LC capacitor CLC, and a section Tb denotes an OFF time during which the TFTs T1 to Tm are turned off when the gate pulse G(N) falls to the threshold voltage Vth. During the section Tb, although the gate pulse G(N) continues to fall, the data pulse D(N) maintains a designated voltage. When the gate pulse G(N) reaches the threshold voltage Vth, the data pulse D(N) starts falling. The falling of data pulse D(N) with the arrival of the gate pulse to the threshold voltage Vth maintains the reliability of the TFTs during their OFF-state operation and prevent noise caused by the next data pulse D(N+1). In other words, the TFTs T1 to Tm remain in the ON state from the time the falling of gate pulse G(N) starts until the gate pulse G(N) reaches the threshold voltage Vth. Depending on the particular characteristics of the TFTs, the TFTs T1 to Tm can be turned ON slightly, although the gate pulse G(N) is under the threshold voltage Vth.
If the falling of the gate pulse and the falling of data pulse occur at the same time, the data pulse D(N+1) corresponding to the next gate line Gm can be applied to the TFTs T1 to Tm before the TFTs T1 to Tm connected to the Gm-1 gate line are turned OFF. Further, the data pulse D(N) can intermix with the data pulse D(N+1), and the LC capacitor CLC can have the noise of mixing two data pulses D(N) and D(N+1). To prevent this phenomenon, the data pulse D(N) maintains the designated voltage during the section Tb after the gate pulse G(N) starts falling. The data pulse D(N) begins to fall after the gate pulse G(N) drops below the threshold voltage Vth; then the TFTs T1 to Tm are all turned OFF.
Comparing FIG. 4A with FIG. 4B, the waveform of the gate pulse G(N) is different between the TFT T1 of FIG. 4 and the TFT Tm of FIG. 4, although the TFT T1 and the TFT Tm are both connected to the same gate line Gm-1. This phenomenon is due to the resistance and capacitance of the conductive gate line 36. The gate pulse G(N) initially applied to the first TFT T1 arrives at the last TFT Tm through the Gm-1 gate line. In other words, since the Gm-1 gate line is conductive and has its own resistance and capacitance, the gate pulse G(N) applied to the Gm-1 gate line is distorted, and the RC delay prolonging the rising and falling times of the gate pulse G(N) occurs between the first TFT T1 and the last TFT Tm. Such an RC delay becomes larger as the resistance of the gate line becomes larger or the length of the gate line becomes longer. In particular, when the falling time of the gate pulse G(N) is prolonged, the image quality of the LCD worsens.
Regarding the Gm-1 gate line, the data pulse D(N) maintains the potential at the time the gate pulse G(N) fails to solve the noise problem of mixing the data pulse D(N+1) applied to the next Gm gate line, and as noted, the data pulse D(N) starts falling after the gate pulse G(N) falls to the threshold voltage Vth of the TFT.
However, as the falling time of the gate pulse becomes longer due to the RC delay, the OFF time Tb reaching the threshold voltage Vth also becomes longer. Therefore, the charging time Ta becomes shorter in order to prevent mixture noise caused by the data line D(N+1) applied to the next Gm gate line. When the charging time Ta is shortened, it also shortens the time to charge the data pulse D(N) in the LC capacitor CLC. As a result, the LC molecules are hardly arranged properly. Moreover, the transmissivity of the LCD deteriorates. The LCD may have reduced brightness, contrast ratio, and resolution. Additionally, the picture displayed may be blurred, or there may be an afterimage and flickering. These phenomena adversely affect the quality of the LCD.
In the related art method to solve the aforementioned problems, the gate line 36 is commonly made of a metallic material having a lower resistance, additional electric circuitry are used to enhance gate modulation, or the gate drivers may be installed at both ends of the gate lines 36. However, these conventional methods increase LCD costs and do not completely solve the various problems caused by RC delay.